Summary: Join a world-class Physical Design team driving macro-level RTL-to-GDSII implementation and signoff for complex SoCs, leading technical strategies and PPA optimization. Highlights: 1. Join a world-class Physical Design team at the forefront of SoC development 2. Drive ground breaking silicon solutions for innovative products 3. Mentor junior engineers and establish best practices in physical design This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Join a world\-class Physical Design team at the forefront of advanced SoC development. Our team is responsible for delivering ground breaking silicon solutions that power innovative products across global markets. With a diverse group of highly skilled engineers, we foster collaboration and technical excellence in a fast\-paced, supportive environment. The team’s work is integral to achieving high\-performance, power\-efficient designs that enable next\-generation technologies. You'll be part of a vibrant, ambitious group passionate about solving complex challenges and driving industry innovation. Your Impact Drive macro\-level RTL\-to\-GDSII physical implementation and signoff for complex SoCs or large subsystem designs, ensuring high\-quality results. Provide technical leadership for architecture\-aware implementation strategies by collaborating closely with Front\-End, RTL, and system teams. Implement end\-to\-end physical design processes—including synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), routing, and signoff convergence—to achieve robust and predictable outcomes. Define and drive PPA (power, performance, area) optimization strategies, ensuring design correctness and reliability. Lead STA, physical and formal verification, EM/IR analysis, and signoff closure to meet advanced\-node reliability and power integrity requirements. Mentor junior engineers, establish best practices, and partner with CAD, methodology, and EDA vendors to improve flows and enable new technologies. Your contributions will directly impact the success of major tapeouts and the adoption of industry\-leading innovations. Minimum Qualifications * Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. * 10\+ years experience in ASIC physical design and implementation. * Proven track record leading physical design preferably for complex SoCs or large IPs through successful tapeout. * Deep expertise in block and top\-level synthesis, place\-and\-route (PnR), timing closure, and signoff. * Experience with industry\-standard implementation and signoff tools (e.g., Synopsys, Cadence). Preferred Qualifications * Demonstrated technical leadership, including mentoring engineers and driving cross\-functional alignment. * Strong understanding of full\-chip integration challenges and RTL\-to\-physical implementation interactions. * Expertise with physical verification (LVS, DRC) and signoff methodologies. * Advanced skills in STA, constraint development, and timing convergence strategies. * Experience driving methodology improvements and collaborating with CAD/flow teams. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.