Summary: Lead DFT architecture development, test planning, and validation for Cisco's silicon products, driving innovation and mentoring junior engineers. Highlights: 1. Advance DFT architecture for robust test planning and development 2. Drive innovation in hardware DFT and test strategies for new silicon models 3. Collaborate cross-functionally to integrate and validate test logic This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Our team is dedicated to advancing DFT architecture to ensure robust test planning and development that supports ATE screening, in\-system testing, debugging, and diagnostics. We collaborate closely with design, design\-verification, and product development teams to integrate and validate test logic throughout implementation and post\-silicon validation phases. Comprising experienced engineers passionate about innovation, our team fosters a collaborative and dynamic environment focused on developing reusable test and debug methodologies for new silicon device models, including bare die and stacked die. What excites us most is driving cutting\-edge hardware DFT strategies and solving complex challenges that directly impact the quality and reliability of Cisco’s silicon products. Your Impact Lead the development and execution of comprehensive test benches to verify DFT architectures, ensuring thorough coverage of design specifications. Collaborate cross\-functionally to integrate test logic and validate it across all implementation stages and post\-silicon validation flows. Drive innovation in hardware DFT and test strategies for emerging silicon device models, promoting reusable methodologies and standards. Identify DFT challenges, facilitate solution brainstorming, and develop implementation plans while mentoring junior engineers to meet project timelines. Your work will directly enhance test coverage, debug efficiency, and product quality, making a significant impact on Cisco’s silicon design and validation processes. Minimum qualifications * Bachelor’s or Master’s Degree in Electrical, Computer Engineering or any relevant field. * 10\+ years of experience in design verification or ASIC design. * Proven experience in test planning based on complex design specifications. * Proficiency in debugging using DVE/Verdi tools. * Experience in scripting languages like Tcl, Python, or Perl. Preferred qualifications * Experience in testbench development using SystemVerilog. * Knowledge of JTAG protocol, scan architecture, MBIST, and boundary scan. * Familiarity with innovative hardware DFT and test strategy development. * Ability to lead and mentor engineers. * Strong problem\-solving skills with minimal mentorship. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.