Summary: Lead macro-level RTL-to-GDSII physical implementation and signoff, collaborating with Front-End teams to deliver complex SoC and block-level projects with technical excellence. Highlights: 1. Lead macro-level RTL-to-GDSII physical implementation and signoff. 2. Collaborate with experienced professionals in physical design. 3. Revolutionize data and infrastructure connection in the AI era at Cisco. This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Our team specializes in macro\-level RTL\-to\-GDSII physical implementation and signoff, collaborating closely with Front\-End teams to ensure optimal results. We are dedicated to delivering complex SoC and block\-level projects through technical excellence and teamwork. The team is composed of highly experienced professionals who value collaboration and high standards in physical design. Your Impact Lead macro\-level RTL\-to\-GDSII physical implementation and signoff. Collaborate with Front\-End teams to translate architecture into optimal physical design. Perform synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing. Optimize power, performance, and area (PPA) while maintaining design correctness through formal verification. Execute static timing analysis (STA), physical verification, formal checks, and signoff closure to ensure reliable, high\-quality silicon. Analyze and resolve Electromigration (EM) and IR\-drop issues to meet reliability and performance signoff targets. Minimum Qualifications * Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. * 6\+ years of hands\-on experience in ASIC design and physical implementation. * Proven track record in ASIC physical design and verification preferably in complex SoC or block\-level projects. * Deep knowledge of block\-level synthesis, place\-and\-route (PnR), and timing closure. * Experience with industry\-standard PnR and signoff tools (e.g., Synopsys, Cadence). Preferred Qualifications * Broad understanding of physical design methodologies, integration, and implementation flows. * Experience in physical verification (LVS, DRC) and signoff processes. * Familiarity with physical design EDA toolchains and end\-to\-end workflows. * Advanced expertise in STA, timing closure, and constraint management. * Proficiency in scripting (Tcl, Python, or Perl) for automation and productivity improvements. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.