Quindio Department Database Development & Administration Job Listings

Indeed

2003237

Meet the Team Join our innovative Analog IC Design team, a dynamic group of engineers dedicated to pushing the boundaries of semiconductor technology. Our work is crucial for developing the foundational analog blocks that power Cisco's next\-generation products, directly impacting our ability to deliver high\-performance and reliable solutions to our customers. Comprising experienced layout and circuit designers, our team fosters a collaborative and energetic environment where new ideas are encouraged, and collective problem\-solving is key. You'll be at the forefront of creating cutting\-edge analog circuits for advanced technology nodes, contributing to products that shape the future of connectivity. Your Impact Design and optimize analog integrated circuit layouts to meet stringent performance, area, and manufacturability requirements. Collaborate closely with circuit designers to translate complex schematics into efficient physical layouts, ensuring compliance with design rules, methodologies, and reliability standards while minimizing parasitic effects. Create detailed analog IC layouts following industry best practices and perform rigorous design rule checks (DRC) and layout versus schematic (LVS) verifications. Optimize layouts for critical factors such as noise reduction, matching, and power efficiency to enhance overall circuit performance. Support tape\-outs on the most advanced manufacturing processes by proactively addressing and resolving layout\-related issues, ensuring successful product realization. Minimum Qualifications * 10\+ years' experience in Analog layout, * Electronics Practical Engineer certificate, a B.Sc. in Electrical Engineering or any relevant field. * Proficiency in layout tools such as Cadence Virtuoso and Calibre DRC/LVS or similar industry\-standard tools. Preferred Qualifications * Experience in advanced technology nodes like 5nm and below, * Strong understanding of analog circuit design and semiconductor device physics, * Ability to work effectively in a team, demonstrating good interpersonal skills, enthusiasm, and positive energy * Excellent communication skills for effective collaboration with cross\-functional teams. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cra. 22 # 27-15, Armenia, Quindío, Colombia

Negotiable Salary

Indeed

1451723

This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Join Cisco’s ASIC Design for Test (DFT) Team, where innovation, collaboration, and technical excellence drive everything we do. As a group of passionate engineers, we are committed to pushing the boundaries of testability and reliability in complex silicon systems. Our mission is to enable robust, high\-quality silicon by architecting and implementing advanced DFT solutions. Working in close partnership with design, verification, and physical implementation teams, we ensure that every Cisco chip is not only powerful, but also rigorously tested and dependable. Here, you’ll play a pivotal role in shaping the future of test engineering while growing alongside some of the best minds in the industry. Your Impact In this role, you will be central to Cisco’s silicon quality and innovation by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability. You will address challenges across digital and mixed\-signal domains, collaborating with multi\-functional teams to design, implement, and optimize sophisticated test solutions. Your work will enhance product robustness, accelerate silicon validation, and drive progress in automated test methodologies. * Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built\-In Self\-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits. * Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed\-signal designs. * Collaborate Across Teams: Work closely with design, verification, ATE, and physical design teams to ensure DFT structures meet functional, timing, and implementation requirements. * Leverage Tools and Automation: Apply and develop automation scripts and in\-house tools for DFT workflows, including MBIST pattern generation and fault simulation, using industry\-standard EDA solutions. * Fault Diagnosis and Debugging: Identify, analyze, and debug issues related to DFT structures, perform root cause analysis on failed tests, and recommend design changes for improved testability. * Documentation and Reporting: Prepare detailed documentation on test plans, test coverage, and debugging results; report on DFT metrics to ensure compliance with company and industry standards. Minimum Qualifications * Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related technical field. * 2\+ years of hands\-on experience in MBIST, SCAN/ATPG, and DFT methodologies for complex digital and mixed\-signal designs. * Proven expertise with industry\-standard DFT tools and flows (e.g., Synopsys, Cadence, Mentor). * Strong understanding of ASIC/FPGA design flow, including RTL design, verification, and test. * Proficiency in scripting languages such as Tcl, Python, or Perl for test automation and workflow enhancement. * Demonstrated ability to identify, analyze, and resolve DFT issues related to MBIST insertion, pattern generation, and fault coverage. * Excellent communication skills and experience collaborating within cross\-functional engineering teams. Preferred Qualifications * Expertise in advanced DFT methodologies such as Logic BIST, Memory BIST, and hybrid scan/MBIST approaches. * Experience with low\-power DFT strategies and power\-aware test techniques. * Ability to develop custom scripts or internal tools for DFT analysis and automation. * Familiarity with industry standards such as IEEE 1149\.1 (JTAG) and IEEE 1500\. * Experience leading DFT efforts on large\-scale projects and mentoring junior engineers. * Strong project management skills and a track record of driving test planning and implementation best practices. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cra. 22 # 27-15, Armenia, Quindío, Colombia

Negotiable Salary

Indeed

1451958

This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands\-on with the Physical Design of intricate chip partitions. Your Impact As a Physical Design CAD Automation Engineer on Cisco’s Silicon One Engineering team, you will develop and maintain automation infrastructure and methodologies to support efficient physical design of advanced ASICs. You will manage IP release and installation, ensuring design teams have access to the latest IP components. Your work will streamline workflows, boost productivity, and enable the delivery of next\-generation networking products, helping Cisco lead in silicon innovation. * Assist with timing constraint development (SDC) and validation for multi\-mode, multi\-corner analysis. * Develop and enhance automation scripts and utilities (TCL, Python) to streamline timing flows and improve engineering efficiency. * Work with senior engineers to support timing closure during the design cycle, assisting with debug and issue triage. * Collaborate with RTL, DFT, and physical design teams to align on design intent and STA best practices. * Assist in the evaluation and deployment of new tool features and methodologies from EDA vendors. * Contribute to documentation, training materials, and internal tool support for design teams. Minimum Qualifications * B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. * 3\+ years of experience in CAD automation or flow development for ASIC Physical Design. * Strong expertise in scripting languages (Tcl, Python, Perl, Shell). * Hands\-on experience with flow automation, EDA integration, and regression systems. * Familiarity with version control (Git, Perforce) and Linux\-based environments. * Excellent debugging, analytical, and communication skills. Preferred Qualifications * Experience supporting IP management, installation, and release processes. * Familiarity with multi\-site and distributed design environments. * Exposure to advanced nodes (7nm, 5nm, 3nm) general EDA flows. * Experience with CI/CD frameworks or automated regression environments for flow validation. * Proficiency with one of key EDA tools such as: Synopsys (Fusion Compiler, PrimeTime, PrimePower), Cadence (Innovus, Tempus, Voltus), Ansys (RedHawk, Totem), Siemens (Calibre DRC/LVS/xRC). Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cra. 22 # 27-15, Armenia, Quindío, Colombia

Negotiable Salary

Indeed

1451704

This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand\-in\-hand with Front\-End teams, we transform cutting\-edge designs into industry\-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity. Your Impact In this role, you'll drive Cisco's silicon innovation by creating breakthrough solutions that blend hardware and software. You'll solve complex challenges, accelerate design processes, and deliver impactful technology. Beyond your technical work, you'll be part of a culture that values mentorship, celebrates success, and supports your growth. This is your opportunity to shape technology that connects and empowers people worldwide. * You will be responsible for macro level RTL to gds implementation and signoff. * Work with Front\-End teams to understand the design architecture to ensure optimal physical implementation. * Execute physical design tasks, including gate\-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing. * Optimize designs to achieve industry\-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification. * Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high\-quality results. * Analyze and resolve Electromigration (EM) and IR\-drop (IR) issues, meeting stringent signoff requirements for reliability and performance. Minimum Qualifications * Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. * 4\+ year minimum of hands\-on experience in ASIC design and verification * Proven expertise in ASIC physical design and verification. * Knowledge of block\-level synthesis, place\-and\-route (PnR), and timing closure. * First\-hand experience with industry\-standard PnR and signoff tools such as Synopsys and Cadence. Preferred Qualifications * Understanding of all aspects of physical design construction, integration, and methodologies. * Proficiency in Physical Design Verification, including techniques like LVS and DRC. * Experience with physical design EDA tools and workflows. * Expertise in Static Timing Analysis (STA), timing closure, and design constraints. * Proficiency in scripting languages like Tcl, Python, or Perl, with a focus on automation and efficiency improvements. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cra. 22 # 27-15, Armenia, Quindío, Colombia

Negotiable Salary

Indeed

1451960

This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high\-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence. Your Impact As part of our team, you’ll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows. You’ll play a key role in enabling the delivery of high\-performance, large\-scale, and complex devices that push the boundaries of what’s possible in chip design. * Develop and refine backend methodologies and flows from RTL to GDS, supporting high\-quality VLSI design. * Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure. * Collaborate with engineering teams to support and enhance implementation tool flows. * Work with advanced silicon technologies and processes to deliver complex and reliable devices. Minimum Requirements * 5\+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience. * B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field. * Strong understanding of STA flows. * Familiarity with PnR, physical verification (PV), and formal verification (FV). Preferred Qualifications * Experience in Physical Design CAD, especially with industry\-standard EDA tools such as Synopsys or Cadence. * Ability to work both independently and within a team. * Strong self\-learning skills and effective communication. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cra. 22 # 27-15, Armenia, Quindío, Colombia

Negotiable Salary

Indeed

1451959

This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands\-on with the Physical Design of intricate chip partitions. Your Impact This role as a Static Timing Analysis (STA) CAD/Methodology Engineer on Cisco’s Silicon One Engineering team offers a key opportunity to enable the next generation of high\-performance networking SoCs and ASICs. You will lead the development of scalable STA flows and automation, enhancing the efficiency and quality of design processes. Working at the intersection of design, methodology, and infrastructure, you will help establish best practices and drive innovation within a leading silicon organization. * Contribute to the development, maintenance, and automation of STA signoff flows for complex SoC designs. * Assist with timing constraint development (SDC) and validation for multi\-mode, multi\-corner analysis. * Develop and enhance automation scripts and utilities (TCL, Python) to streamline timing flows and improve engineering efficiency. * Work with senior engineers to support timing closure during the design cycle, assisting with debug and issue triage. * Collaborate with RTL, DFT, and physical design teams to align on design intent and STA best practices. * Assist in the evaluation and deployment of new tool features and methodologies from EDA vendors. * Contribute to documentation, training materials, and internal tool support for design teams. Minimum Qualifications * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. * 4\+ years of experience in ASIC or SoC design with a focus on STA, CAD automation, or physical design methodology. * Solid understanding of STA fundamentals: setup/hold, clock skew, OCV, path exceptions, MMMC analysis. * Experience using timing tools such as PrimeTime, Tempus, or similar. * Proficient in scripting languages such as TCL and Python. * Familiarity with physical design flows, synthesis, and timing ECOs is preferred. * Strong analytical and problem\-solving skills with attention to detail. * A team player with good communication skills and a collaborative attitude. Preferred Qualifications * Exposure to large\-scale SoC design flows, especially in networking or communications domains. * Experience working in a Unix/Linux\-based development environment. * Knowledge of EDA tool environments, job scheduling systems, or version control systems (e.g., Git, Perforce). * Enthusiasm for continuous learning and improving automation and productivity. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cra. 22 # 27-15, Armenia, Quindío, Colombia

Negotiable Salary

Indeed

1451703

This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand\-in\-hand with Front\-End teams, we transform cutting\-edge designs into industry\-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity. Your Impact In this role, you'll drive Cisco's silicon innovation by creating breakthrough solutions that blend hardware and software. You'll solve complex challenges, accelerate design processes, and deliver impactful technology. Beyond your technical work, you'll be part of a culture that values mentorship, celebrates success, and supports your growth. This is your opportunity to shape technology that connects and empowers people worldwide. * You will be responsible for macro level RTL to GDS implementation and signoff. * Work with Front\-End teams to understand the design architecture to ensure optimal physical implementation. * Execute physical design tasks, including gate\-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing. * Optimize designs to achieve industry\-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification. * Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high\-quality results. * Analyze and resolve Electromigration (EM) and IR\-drop (IR) issues, meeting stringent signoff requirements for reliability and performance. Minimum Qualifications * Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. * 4\+ year minimum of hands\-on experience in ASIC design and verification * Proven expertise in ASIC physical design and verification. * Knowledge of block\-level synthesis, place\-and\-route (PnR), and timing closure. * First\-hand experience with industry\-standard PnR and signoff tools such as Synopsys and Cadence. Preferred Qualifications * Understanding of all aspects of physical design construction, integration, and methodologies. * Proficiency in Physical Design Verification, including techniques like LVS and DRC. * Experience with physical design EDA tools and workflows. * Expertise in Static Timing Analysis (STA), timing closure, and design constraints. * Proficiency in scripting languages like Tcl, Python, or Perl, with a focus on automation and efficiency improvements. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cra. 22 # 27-15, Armenia, Quindío, Colombia

Negotiable Salary

Indeed

1451957

This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands\-on with the Physical Design of intricate chip partitions. Your Impact This role as a Static Timing Analysis (STA) CAD/Methodology Engineer on Cisco’s Silicon One Engineering team offers a key opportunity to enable the next generation of high\-performance networking SoCs and ASICs. You will lead the development of scalable STA flows and automation, enhancing the efficiency and quality of design processes. Working at the intersection of design, methodology, and infrastructure, you will help establish best practices and drive innovation within a leading silicon organization. * Architect, develop, and maintain static timing analysis (STA) methodologies and flows to support full\-chip and hierarchical signoff for high\-speed networking ASICs. * Support timing closure for SoCs with complex clocking structures, high\-speed interfaces, and large\-scale integration. * Develop robust SDC management, checking, and validation infrastructure across multi\-mode, multi\-corner (MMMC) scenarios. * Build and optimize automation scripts and infrastructure (TCL, Python, Makefiles, etc.) to scale timing flows for enterprise\-level SoC programs. * Collaborate with RTL design, DFT, P, and signoff teams to align on timing methodologies and resolve critical timing issues. * Work with EDA vendors to drive tool evaluations, enhancements, and roadmap discussions. * Drive flow standardization across business units and participate in timing methodology governance across global CAD teams. Minimum Qualifications * B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. * 6\+ years of experience in ASIC/SoC timing analysis, CAD flow development, or physical design methodology. * Expertise in STA fundamentals, including setup/hold, skew, OCV/AOCV/POCV, CRPR, and noise analysis. * Proficiency with industry\-standard tools such as Synopsys PrimeTime, Cadence Tempus, or equivalent. * Strong scripting experience in TCL, Python, and automation frameworks. * First\-hand experience with timing constraint (SDC) creation, management, and validation. * Solid understanding of physical implementation flows (synthesis, floorplanning, P, timing ECO). * Experience with large\-scale SoC programs and hierarchical timing signoff flows. Preferred Qualifications * Familiarity with networking ASIC design challenges (e.g., low latency, high\-throughput clocking, SerDes, packet processors) is a strong plus. * Strong communicator and team player, able to work across geographically distributed teams. * Exposure to networking ASIC architectures, high\-speed interface timing, and power\-aware timing flows. * Experience with liberty modeling, timing model generation, and correlation to silicon. * Familiarity with version control systems (e.g., Git/Perforce), and job schedulers (LSF/SLURM). * Prior experience in a large enterprise engineering organization or global silicon team is a plus. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cra. 22 # 27-15, Armenia, Quindío, Colombia

Negotiable Salary

ADMINISTRATIVE AND ACCOUNTING ASSISTANT64142905511297128

Indeed

ADMINISTRATIVE AND ACCOUNTING ASSISTANT

**Position Purpose** Provide comprehensive support in the administrative and accounting processes of the organization, ensuring proper document management, timely recording of financial information, and assistance to different departments in coordination, control, and reporting tasks. This role is key to ensuring operational efficiency and compliance with accounting and administrative obligations. **Main Responsibilities** * Support the recording, control, and verification of accounting transactions in information systems. * Prepare and follow up on invoices, accounting vouchers, reconciliations, and financial reports. * Maintain updated and organized accounting, administrative, and document management files. * Assist in preparing accounting and administrative reports for management. * Manage internal and external communications, schedule meetings, coordinate agendas, and track commitments. * Handle and update databases in Excel, generating reports, comparative tables, and data analysis. * Use **office software** (Word, Excel, PowerPoint, Outlook, etc.) (advanced Excel skills) for document management, presentations, and reporting. * Implement and utilize **Artificial Intelligence** tools and automation to optimize administrative processes and data analysis. * Provide support in procurement processes, supplier management, and payments according to internal policies. * Assist in internal and external audits when required. Job Type: Full-time

Cl. 21 #8-72, Pereira, Risaralda, Colombia

Negotiable Salary

Indeed

Development Engineer

A **certified Great Place To Work** company and leader in the Coffee Region is looking for our next **Development Engineer**. Your mission will be to **design, develop, and integrate software solutions** that drive efficiency and digital transformation within our technological ecosystem. What are we looking for? **Education:** Professional degree in Systems Engineering, Data Engineering, or related fields to Software Development or mobile applications. **Experience:** Minimum of **2 proven years** in software development projects and data analytics units. Tools: GitHub, Jira, Mantis. Technical skills Languages: **PHP (v7\+), Laravel (v5\+), Python or C\#** Databases: **MySQL, SQL Server** **APIs, Web Services, version control, and documentation** Basic knowledge of **infrastructure for environment setup** (Desirable) Experience in **mobile development** Position conditions **Contract:** Initially project-based. **Working hours:** Monday to Friday **Salary:** Negotiable. If you are passionate about technology, innovation, and teamwork, this is your opportunity! Apply now and become part of a company that **believes in its people and transforms through technology**. **\#TalentoCercafe \#GreatPlaceToWork \#Engineering \#SoftwareDevelopment \#CoffeeRegion** Job type: Full-time

Cl. 21 #8-72, Pereira, Risaralda, Colombia

Negotiable Salary