Memory Layout Design Engineer

Description

Summary: This role involves implementing high-quality memory layout for the Cisco Silicon One platform, collaborating with international circuit design teams to deliver groundbreaking silicon solutions. Highlights: 1. Work at the forefront of innovation in high-performance networking technology. 2. Collaborate with international circuit design teams on physical designs. 3. Optimize layout designs for quality, visibility, and velocity. This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Our team is at the forefront of innovation, specializing in memory layout implementation for the Cisco Silicon One platform that powers the world’s most advanced switches and routers. We are a dynamic, international team dedicated to pushing the boundaries of high\-performance networking technology. We offer a unique environment where technical excellence meets real\-world impact. We value transparency, clear communication, and a collaborative spirit that bridges geographical divides to deliver ground breaking silicon solutions. Your Impact Implement high\-quality memory layout implementation, specifically focusing on SRAM blocks to meet rigorous performance and reliability standards. Collaborate closely with international circuit design teams to translate schematics into robust physical designs that drive our core networking products. Perform post\-layout simulations and implement necessary corrections to ensure DRC cleanliness and optimal integration with neighboring modules. Optimize layout designs for quality, visibility, and velocity to accelerate the delivery of critical silicon components. Minimum Qualifications * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. * 4\+ years of total professional experience in physical design or layout. * Proven experience working with industry\-standard EDA tools such as Cadence or Synopsys. * Experience with advanced node technologies such as TSMC 22nm, 12nm, 7nm, 5nm, or 2nm. Preferred Qualifications * Experience working within a mixed\-signal or custom design environment. * Experience in performing EMIR/ERC closure and providing technical support for successful tapeouts. * Background in circuit design, including reading schematics and running simulations. * Knowledge in scripting languages (Tcl, Python, or Perl) for design automation. * Strong ability to communicate effectively in English, both written and spoken, to support international collaboration. * Demonstrated ability to work both independently and within a cross\-functional, multi\-site team environment. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.