Summary: Join the Silicon One development organization as a key member, driving high-quality Design for Test (DFT) verification and contributing to groundbreaking solutions in networking silicon. Highlights: 1. Contribute to groundbreaking solutions shaping the future of networking silicon 2. Collaborate with Front-end RTL and backend physical design teams 3. Drive high-quality Design for Test (DFT) verification This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team The Common Hardware Group delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. The team designs networking hardware for Enterprises, Service Providers, the Public Sector, and Non\-Profit Organizations worldwide. Cisco Silicon One (\#CiscoSiliconOne) is the only unifying silicon architecture in the market, enabling customers to deploy best\-of\-breed silicon from TOR switches through web\-scale data centers and across service provider and enterprise networks with a fully unified routing and switching portfolio. The team is composed of highly skilled engineers working on some of the most complex ASICs in the industry, fostering a collaborative and innovative environment. Joining this team means contributing to groundbreaking solutions that shape the future of networking silicon. Your Impact You will be a key member of the Silicon One development organization, collaborating closely with Front\-end RTL and backend physical design teams to deeply understand chip architecture. Drive high\-quality Design for Test (DFT) verification to ensure robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation. Take part in all aspects of digital design, from micro\-architecture to RTL design and qualification. Integrate and verify sub\-systems/SoCs, review and enhance RTL codes, and improve flows and methodologies to streamline IP/SoC development and integration. Work closely with the verification team for complex debug and resolution of verification failures, and interact with the physical design team to achieve better physical design Quality of Results (QoR). Minimum Qualifications * 5\+ years of industry experience in ASIC digital design. * Proficient in Verilog/System Verilog coding. * Experience with front\-end tools such as Verilog simulators, linting, CDC checkers, synthesis, and formal verification. * Proficiency to use at least one scripting language (Python, Tcl, and Make). * Fluency in English, both spoken and written. Preferred Qualifications * Familiarity with ASIC development flow. * Experience with industry\-standard interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories. * Familiarity with power optimization techniques, power intent (UPF), and power estimation. * Familiarity with DFT/MBIST is a plus. * Good communication skills, self\-motivated, and well\-organized. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.